CVE-2025-0647 json
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to t…
published 2026-01-14 9 mo ago modified 2026-06-17 4 mo ago also EUVD-2026-2516
- cvss
- 7.9
- version 3.1, CNA
- cisa kev
- Not listed
- not in CISA's catalog
- epss
- 0.2%
- EPSS 0.2% chance of exploitation in 30 days, percentile 5%
- public exploits
- 0
- none known
Summary
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Patch / fix
- arm-trusted-firmware Debian 14 2.12.16+dfsg-1
debian advisories DEBIAN-CVE-2025-0647
CISA SSVC
- Exploitation
- none
- Automatable
- no
- Technical impact
- total
- Assessed
- 9 mo ago
Exploit prediction
0.17% chance of exploitation in the next 30 days, higher than 5% of all scored CVEs (FIRST EPSS, 2026-11-08).
CVSS scores
| assigned by | version | score | vector |
|---|---|---|---|
| CISA ADP | 3.1 | 7.9 | CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N |
| CNA | 3.1 | 7.9 | CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N |
Affected products
- Arm Neoverse-N2
- Arm Neoverse-V3AE
- Arm Neoverse-V3
- Arm Neoverse-V2
- Arm Cortex-X925
- Arm Cortex-X4
- Arm Cortex-X3
- Arm Cortex-X2
- Arm Cortex-A710
- Arm C1-Premium
- Arm C1-Ultra
Classification
- Weakness
-
- CWE-226 Sensitive Information in Resource Not Removed Before Reuse
References
-
developer.arm.com
/documentation/111546
vendor-advisory
-
graph.volerion.com
/view?ID=CVE-2025-0647
third-party-advisory
Sources
- CVE List CVE-2025-0647
- NVD CVE-2025-0647
Fencer Vulns keeps one entry per vulnerability: the CVE id wins, then GHSA, and records that alias each other are merged, except that two CVEs always keep separate entries. The same data is available as JSON.