Side-channels Related to the x86 PREFETCH Instruction

published 2021-10-13 5 y ago modified 2026-06-17 4 mo ago also EUVD-2021-13124

cvss: 4.7; version 3.1, NVD
cisa kev: Not listed; not in CISA's catalog
epss: 0.3%; EPSS 0.3% chance of exploitation in 30 days, percentile 25%
public exploits: 0; none known

A timing and power-based side channel attack leveraging the x86 PREFETCH instructions on some AMD CPUs could potentially result in leaked kernel address space information.

Patch / fix

distros 1

spectre-meltdown-checker openSUSE Tumbleweed 26.36.0602723-1.1

opensuse advisories openSUSE-SU-2026:11242-1

Exploit prediction

0.33% chance of exploitation in the next 30 days, higher than 25% of all scored CVEs (FIRST EPSS, 2026-11-08).

CVSS scores

assigned by	version	score	vector
NVD	3.1	4.7	CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:N/A:N
NVD	2.0	1.9	AV:L/AC:M/Au:N/C:P/I:N/A:N

Affected products

AMD All supported processors

Classification

Weakness

CWE-208 Observable Timing Discrepancy
CWE-203 Observable Discrepancy

References

amd.com /en/corporate/product-security/bulletin/amd-sb-1017
vendor-advisory

Sources

CVE List CVE-2021-26318
NVD CVE-2021-26318

Fencer Vulns keeps one entry per vulnerability: the CVE id wins, then GHSA, and records that alias each other are merged, except that two CVEs always keep separate entries. The same data is available as JSON.

Summary